cli/q
Code Issues 1 Pull Requests Activity

Added register documentation for arm64

Browse Source
This commit is contained in:
Eduard Urbach
2025-03-23 12:57:05 +01:00
parent 597eb08ff6
commit ae928156c5
2 changed files with 33 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
src/arm/Registers.go
View File

@ -3,7 +3,7 @@ package arm
import "git.urbach.dev/cli/q/src/cpu" import "git.urbach.dev/cli/q/src/cpu"
const ( const (
X0 cpu.Register = iota X0 cpu.Register = iota // Function arguments and return values [0-7]
X1 X1
X2 X2
X3 X3
@ -11,18 +11,18 @@ const (
X5 X5
X6 X6
X7 X7
X8 X8 // Indirect result location register (used to pass a pointer to a structure return value)
X9 X9 // Temporary registers (caller-saved, used for general computation) [9-15]
X10 X10
X11 X11
X12 X12
X13 X13
X14 X14
X15 X15
X16 X16 // Intra-procedure call scratch registers [16-17]
X17 X17
X18 X18 // Platform register (reserved by the platform ABI for thread-local storage)
X19 X19 // Callee-saved registers (must be preserved across function calls) [19-28]
X20 X20
X21 X21
X22 X22
@ -32,14 +32,18 @@ const (
X26 X26
X27 X27
X28 X28
FP // Frame pointer FP // Frame pointer
LR // Link register LR // Link register
SP // Stack pointer SP // Stack pointer
ZR = SP // Zero register uses the same numerical value as SP )
const (
ZR = SP // Zero register uses the same numerical value as SP
TMP = X28 // Temporary register for the assembler
) )
var ( var (
GeneralRegisters = []cpu.Register{X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28} GeneralRegisters = []cpu.Register{X9, X10, X11, X12, X13, X14, X15, X16, X17, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28}
InputRegisters = []cpu.Register{X0, X1, X2, X3, X4, X5} InputRegisters = []cpu.Register{X0, X1, X2, X3, X4, X5}
OutputRegisters = InputRegisters OutputRegisters = InputRegisters
SyscallInputRegisters = []cpu.Register{X8, X0, X1, X2, X3, X4, X5} SyscallInputRegisters = []cpu.Register{X8, X0, X1, X2, X3, X4, X5}

45
src/asmc/ARM.go
View File

@ -113,9 +113,8 @@ func (c *compiler) ARM(x asm.Instruction) {
operands := c.assembler.Param.MemoryNumber[x.Index] operands := c.assembler.Param.MemoryNumber[x.Index]
if operands.Address.OffsetRegister < 0 { if operands.Address.OffsetRegister < 0 {
tmp := arm.X28 c.code = arm.MoveRegisterNumber(c.code, arm.TMP, operands.Number)
c.code = arm.MoveRegisterNumber(c.code, tmp, operands.Number) c.append(arm.StoreRegister(arm.TMP, operands.Address.Base, int(operands.Address.Offset), operands.Address.Length))
c.append(arm.StoreRegister(tmp, operands.Address.Base, int(operands.Address.Offset), operands.Address.Length))
} else { } else {
panic("not implemented") panic("not implemented")
} }
@ -155,9 +154,8 @@ func (c *compiler) ARM(x asm.Instruction) {
if encodable { if encodable {
c.append(code) c.append(code)
} else { } else {
tmp := arm.X28 c.code = arm.MoveRegisterNumberMI(c.code, arm.TMP, operand.Number)
c.code = arm.MoveRegisterNumberMI(c.code, tmp, operand.Number) c.append(arm.AndRegisterRegister(operand.Register, operand.Register, arm.TMP))
c.append(arm.AndRegisterRegister(operand.Register, operand.Register, tmp))
} }
case asm.TypeRegisterRegister: case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index] operand := c.assembler.Param.RegisterRegister[x.Index]
@ -173,9 +171,8 @@ func (c *compiler) ARM(x asm.Instruction) {
if encodable { if encodable {
c.append(code) c.append(code)
} else { } else {
tmp := arm.X28 c.code = arm.MoveRegisterNumberMI(c.code, arm.TMP, operand.Number)
c.code = arm.MoveRegisterNumberMI(c.code, tmp, operand.Number) c.append(arm.OrRegisterRegister(operand.Register, operand.Register, arm.TMP))
c.append(arm.OrRegisterRegister(operand.Register, operand.Register, tmp))
} }
case asm.TypeRegisterRegister: case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index] operand := c.assembler.Param.RegisterRegister[x.Index]
@ -191,9 +188,8 @@ func (c *compiler) ARM(x asm.Instruction) {
if encodable { if encodable {
c.append(code) c.append(code)
} else { } else {
tmp := arm.X28 c.code = arm.MoveRegisterNumberMI(c.code, arm.TMP, operand.Number)
c.code = arm.MoveRegisterNumberMI(c.code, tmp, operand.Number) c.append(arm.XorRegisterRegister(operand.Register, operand.Register, arm.TMP))
c.append(arm.XorRegisterRegister(operand.Register, operand.Register, tmp))
} }
case asm.TypeRegisterRegister: case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index] operand := c.assembler.Param.RegisterRegister[x.Index]
@ -209,9 +205,8 @@ func (c *compiler) ARM(x asm.Instruction) {
if encodable { if encodable {
c.append(code) c.append(code)
} else { } else {
tmp := arm.X28 c.code = arm.MoveRegisterNumber(c.code, arm.TMP, operand.Number)
c.code = arm.MoveRegisterNumber(c.code, tmp, operand.Number) c.append(arm.AddRegisterRegister(operand.Register, operand.Register, arm.TMP))
c.append(arm.AddRegisterRegister(operand.Register, operand.Register, tmp))
} }
case asm.TypeRegisterRegister: case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index] operand := c.assembler.Param.RegisterRegister[x.Index]
@ -227,9 +222,8 @@ func (c *compiler) ARM(x asm.Instruction) {
if encodable { if encodable {
c.append(code) c.append(code)
} else { } else {
tmp := arm.X28 c.code = arm.MoveRegisterNumber(c.code, arm.TMP, operand.Number)
c.code = arm.MoveRegisterNumber(c.code, tmp, operand.Number) c.append(arm.SubRegisterRegister(operand.Register, operand.Register, arm.TMP))
c.append(arm.SubRegisterRegister(operand.Register, operand.Register, tmp))
} }
case asm.TypeRegisterRegister: case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index] operand := c.assembler.Param.RegisterRegister[x.Index]
@ -245,9 +239,8 @@ func (c *compiler) ARM(x asm.Instruction) {
if encodable { if encodable {
c.append(code) c.append(code)
} else { } else {
tmp := arm.X28 c.code = arm.MoveRegisterNumber(c.code, arm.TMP, operand.Number)
c.code = arm.MoveRegisterNumber(c.code, tmp, operand.Number) c.append(arm.CompareRegisterRegister(operand.Register, arm.TMP))
c.append(arm.CompareRegisterRegister(operand.Register, tmp))
} }
case asm.TypeRegisterRegister: case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index] operand := c.assembler.Param.RegisterRegister[x.Index]
@ -270,18 +263,16 @@ func (c *compiler) ARM(x asm.Instruction) {
c.append(arm.MulRegisterRegister(operand.Destination, operand.Destination, operand.Source)) c.append(arm.MulRegisterRegister(operand.Destination, operand.Destination, operand.Source))
case asm.TypeRegisterNumber: case asm.TypeRegisterNumber:
operand := c.assembler.Param.RegisterNumber[x.Index] operand := c.assembler.Param.RegisterNumber[x.Index]
tmp := arm.X28 c.code = arm.MoveRegisterNumber(c.code, arm.TMP, operand.Number)
c.code = arm.MoveRegisterNumber(c.code, tmp, operand.Number) c.append(arm.MulRegisterRegister(operand.Register, operand.Register, arm.TMP))
c.append(arm.MulRegisterRegister(operand.Register, operand.Register, tmp))
} }
case asm.MODULO: case asm.MODULO:
switch x.Type { switch x.Type {
case asm.TypeRegisterRegister: case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index] operand := c.assembler.Param.RegisterRegister[x.Index]
tmp := arm.X28 c.append(arm.DivSigned(arm.TMP, operand.Destination, operand.Source))
c.append(arm.DivSigned(tmp, operand.Destination, operand.Source)) c.append(arm.MultiplySubtract(operand.Destination, arm.TMP, operand.Source, operand.Destination))
c.append(arm.MultiplySubtract(operand.Destination, tmp, operand.Source, operand.Destination))
case asm.TypeRegisterNumber: case asm.TypeRegisterNumber:
panic("not implemented") panic("not implemented")
} }