Implemented bitwise operations on arm64

src/arm/And.go

@@ -5,14 +5,9 @@ import (
 )
 
 // AndRegisterNumber performs a bitwise AND using a register and a number.
-func AndRegisterNumber(destination cpu.Register, source cpu.Register, number int) uint32 {
+func AndRegisterNumber(destination cpu.Register, source cpu.Register, number int) (uint32, bool) {
 	imm13, encodable := encodeLogicalImmediate(uint(number))
-
+	return 0b100100100<<23 | reg2BitmaskImm(destination, source, imm13), encodable
-	if !encodable {
-		panic("bitwise and operand can't be encoded as a bitmask immediate")
-	}
-
-	return 0b100100100<<23 | uint32(imm13)<<10 | reg2(destination, source)
 }
 
 // AndRegisterRegister performs a bitwise AND using two registers.

src/arm/And_test.go

@@ -25,7 +25,8 @@ func TestAndRegisterNumber(t *testing.T) {
 
 	for _, pattern := range usagePatterns {
 		t.Logf("and %s, %s, %d", pattern.Destination, pattern.Source, pattern.Number)
-		code := arm.AndRegisterNumber(pattern.Destination, pattern.Source, pattern.Number)
+		code, encodable := arm.AndRegisterNumber(pattern.Destination, pattern.Source, pattern.Number)
+		assert.True(t, encodable)
 		assert.DeepEqual(t, code, pattern.Code)
 	}
 }

src/arm/Move.go

@@ -10,7 +10,7 @@ func MoveRegisterRegister(destination cpu.Register, source cpu.Register) uint32
 		return AddRegisterNumber(destination, source, 0)
 	}
 
-	return 0b10101010<<24 | reg3(destination, ZR, source)
+	return OrRegisterRegister(destination, ZR, source)
 }
 
 // MoveRegisterNumber moves an integer into the given register.

src/arm/Or.go

@@ -0,0 +1,14 @@
+package arm
+
+import "git.urbach.dev/cli/q/src/cpu"
+
+// OrRegisterNumber performs a bitwise OR using a register and a number.
+func OrRegisterNumber(destination cpu.Register, source cpu.Register, number int) (uint32, bool) {
+	imm13, encodable := encodeLogicalImmediate(uint(number))
+	return 0b101100100<<23 | reg2BitmaskImm(destination, source, imm13), encodable
+}
+
+// OrRegisterRegister performs a bitwise OR using two registers.
+func OrRegisterRegister(destination cpu.Register, source cpu.Register, operand cpu.Register) uint32 {
+	return 0b10101010<<24 | reg3(destination, source, operand)
+}

src/arm/Or_test.go

@@ -0,0 +1,49 @@
+package arm_test
+
+import (
+	"testing"
+
+	"git.urbach.dev/cli/q/src/arm"
+	"git.urbach.dev/cli/q/src/cpu"
+	"git.urbach.dev/go/assert"
+)
+
+func TestOrRegisterNumber(t *testing.T) {
+	usagePatterns := []struct {
+		Destination cpu.Register
+		Source      cpu.Register
+		Number      int
+		Code        uint32
+	}{
+		{arm.X0, arm.X1, 1, 0xB2400020},
+		{arm.X0, arm.X1, 2, 0xB27F0020},
+		{arm.X0, arm.X1, 3, 0xB2400420},
+		{arm.X0, arm.X1, 7, 0xB2400820},
+		{arm.X0, arm.X1, 16, 0xB27C0020},
+		{arm.X0, arm.X1, 255, 0xB2401C20},
+	}
+
+	for _, pattern := range usagePatterns {
+		t.Logf("orr %s, %s, %d", pattern.Destination, pattern.Source, pattern.Number)
+		code, encodable := arm.OrRegisterNumber(pattern.Destination, pattern.Source, pattern.Number)
+		assert.True(t, encodable)
+		assert.DeepEqual(t, code, pattern.Code)
+	}
+}
+
+func TestOrRegisterRegister(t *testing.T) {
+	usagePatterns := []struct {
+		Destination cpu.Register
+		Source      cpu.Register
+		Operand     cpu.Register
+		Code        uint32
+	}{
+		{arm.X0, arm.X1, arm.X2, 0xAA020020},
+	}
+
+	for _, pattern := range usagePatterns {
+		t.Logf("orr %s, %s, %s", pattern.Destination, pattern.Source, pattern.Operand)
+		code := arm.OrRegisterRegister(pattern.Destination, pattern.Source, pattern.Operand)
+		assert.DeepEqual(t, code, pattern.Code)
+	}
+}

src/arm/Xor.go

@@ -0,0 +1,14 @@
+package arm
+
+import "git.urbach.dev/cli/q/src/cpu"
+
+// XorRegisterNumber performs a bitwise XOR using a register and a number.
+func XorRegisterNumber(destination cpu.Register, source cpu.Register, number int) (uint32, bool) {
+	imm13, encodable := encodeLogicalImmediate(uint(number))
+	return 0b110100100<<23 | reg2BitmaskImm(destination, source, imm13), encodable
+}
+
+// XorRegisterRegister performs a bitwise XOR using two registers.
+func XorRegisterRegister(destination cpu.Register, source cpu.Register, operand cpu.Register) uint32 {
+	return 0b11001010<<24 | reg3(destination, source, operand)
+}

src/arm/Xor_test.go

@@ -0,0 +1,49 @@
+package arm_test
+
+import (
+	"testing"
+
+	"git.urbach.dev/cli/q/src/arm"
+	"git.urbach.dev/cli/q/src/cpu"
+	"git.urbach.dev/go/assert"
+)
+
+func TestXorRegisterNumber(t *testing.T) {
+	usagePatterns := []struct {
+		Destination cpu.Register
+		Source      cpu.Register
+		Number      int
+		Code        uint32
+	}{
+		{arm.X0, arm.X1, 1, 0xD2400020},
+		{arm.X0, arm.X1, 2, 0xD27F0020},
+		{arm.X0, arm.X1, 3, 0xD2400420},
+		{arm.X0, arm.X1, 7, 0xD2400820},
+		{arm.X0, arm.X1, 16, 0xD27C0020},
+		{arm.X0, arm.X1, 255, 0xD2401C20},
+	}
+
+	for _, pattern := range usagePatterns {
+		t.Logf("eor %s, %s, %d", pattern.Destination, pattern.Source, pattern.Number)
+		code, encodable := arm.XorRegisterNumber(pattern.Destination, pattern.Source, pattern.Number)
+		assert.True(t, encodable)
+		assert.DeepEqual(t, code, pattern.Code)
+	}
+}
+
+func TestXorRegisterRegister(t *testing.T) {
+	usagePatterns := []struct {
+		Destination cpu.Register
+		Source      cpu.Register
+		Operand     cpu.Register
+		Code        uint32
+	}{
+		{arm.X0, arm.X1, arm.X2, 0xCA020020},
+	}
+
+	for _, pattern := range usagePatterns {
+		t.Logf("eor %s, %s, %s", pattern.Destination, pattern.Source, pattern.Operand)
+		code := arm.XorRegisterRegister(pattern.Destination, pattern.Source, pattern.Operand)
+		assert.DeepEqual(t, code, pattern.Code)
+	}
+}

src/arm/encode.go

@@ -37,6 +37,11 @@ func reg2Imm(d cpu.Register, n cpu.Register, imm12 int) uint32 {
 	return uint32(imm12&mask12)<<10 | uint32(n)<<5 | uint32(d)
 }
 
+// reg2BitmaskImm encodes an instruction with 2 registers and a bitmask immediate.
+func reg2BitmaskImm(d cpu.Register, n cpu.Register, imm13 int) uint32 {
+	return uint32(imm13)<<10 | uint32(n)<<5 | uint32(d)
+}
+
 // reg3 encodes an instruction with 3 registers.
 func reg3(d cpu.Register, n cpu.Register, m cpu.Register) uint32 {
 	return uint32(m)<<16 | uint32(n)<<5 | uint32(d)

src/asmc/compileARM.go

@@ -99,6 +99,60 @@ func (c *compiler) compileARM(x asm.Instruction) {
 			c.append(arm.AddRegisterNumber(arm.SP, arm.SP, 16))
 		}
 
+	case asm.AND:
+		switch x.Type {
+		case asm.TypeRegisterNumber:
+			operand := c.assembler.Param.RegisterNumber[x.Index]
+			code, encodable := arm.AndRegisterNumber(operand.Register, operand.Register, operand.Number)
+
+			if encodable {
+				c.append(code)
+			} else {
+				tmp := arm.X28
+				c.append(arm.MoveRegisterNumber(tmp, operand.Number))
+				c.append(arm.AndRegisterRegister(operand.Register, operand.Register, tmp))
+			}
+		case asm.TypeRegisterRegister:
+			operand := c.assembler.Param.RegisterRegister[x.Index]
+			c.append(arm.AndRegisterRegister(operand.Destination, operand.Destination, operand.Source))
+		}
+
+	case asm.OR:
+		switch x.Type {
+		case asm.TypeRegisterNumber:
+			operand := c.assembler.Param.RegisterNumber[x.Index]
+			code, encodable := arm.OrRegisterNumber(operand.Register, operand.Register, operand.Number)
+
+			if encodable {
+				c.append(code)
+			} else {
+				tmp := arm.X28
+				c.append(arm.MoveRegisterNumber(tmp, operand.Number))
+				c.append(arm.OrRegisterRegister(operand.Register, operand.Register, tmp))
+			}
+		case asm.TypeRegisterRegister:
+			operand := c.assembler.Param.RegisterRegister[x.Index]
+			c.append(arm.OrRegisterRegister(operand.Destination, operand.Destination, operand.Source))
+		}
+
+	case asm.XOR:
+		switch x.Type {
+		case asm.TypeRegisterNumber:
+			operand := c.assembler.Param.RegisterNumber[x.Index]
+			code, encodable := arm.XorRegisterNumber(operand.Register, operand.Register, operand.Number)
+
+			if encodable {
+				c.append(code)
+			} else {
+				tmp := arm.X28
+				c.append(arm.MoveRegisterNumber(tmp, operand.Number))
+				c.append(arm.XorRegisterRegister(operand.Register, operand.Register, tmp))
+			}
+		case asm.TypeRegisterRegister:
+			operand := c.assembler.Param.RegisterRegister[x.Index]
+			c.append(arm.XorRegisterRegister(operand.Destination, operand.Destination, operand.Source))
+		}
+
 	case asm.ADD:
 		switch x.Type {
 		case asm.TypeRegisterNumber: