From 3fa3ff9227654ef3b5f9202edda4da8b311319f5 Mon Sep 17 00:00:00 2001 From: Eduard Urbach Date: Sun, 18 Aug 2024 09:52:45 +0200 Subject: [PATCH] Added more RISC-V registers --- src/arch/riscv/Registers.go | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/arch/riscv/Registers.go b/src/arch/riscv/Registers.go index 5267be3..66bf189 100644 --- a/src/arch/riscv/Registers.go +++ b/src/arch/riscv/Registers.go @@ -37,4 +37,7 @@ const ( X31 ) -var SyscallInputRegisters = []cpu.Register{X10, X11, X12, X13, X14, X15, X16} +var ( + SyscallInputRegisters = []cpu.Register{X17, X10, X11, X12, X13, X14, X15, X16} + SyscallOutputRegisters = []cpu.Register{X10, X11} +)