Simplified code

This commit is contained in:
Eduard Urbach 2024-07-30 12:20:33 +02:00
parent ae8e46de4d
commit 265ab988d9
Signed by: akyoto
GPG Key ID: C874F672B1AF20C0
3 changed files with 26 additions and 17 deletions

View File

@ -0,0 +1,13 @@
package core
import (
"fmt"
)
// AddBytes adds a sequence of bytes and returns its address as a label.
func (f *Function) AddBytes(value []byte) string {
f.count.data++
label := fmt.Sprintf("%s_data_%d", f.Name, f.count.data)
f.Assembler.SetData(label, value)
return label
}

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@ -8,37 +8,37 @@ import (
) )
// ExecuteRegisterRegister performs an operation on two registers. // ExecuteRegisterRegister performs an operation on two registers.
func (f *Function) ExecuteRegisterRegister(operation token.Token, destination cpu.Register, source cpu.Register) error { func (f *Function) ExecuteRegisterRegister(operation token.Token, register cpu.Register, operand cpu.Register) error {
switch operation.Kind { switch operation.Kind {
case token.Add, token.AddAssign: case token.Add, token.AddAssign:
f.RegisterRegister(asm.ADD, destination, source) f.RegisterRegister(asm.ADD, register, operand)
case token.Sub, token.SubAssign: case token.Sub, token.SubAssign:
f.RegisterRegister(asm.SUB, destination, source) f.RegisterRegister(asm.SUB, register, operand)
case token.Mul, token.MulAssign: case token.Mul, token.MulAssign:
f.RegisterRegister(asm.MUL, destination, source) f.RegisterRegister(asm.MUL, register, operand)
case token.Div, token.DivAssign: case token.Div, token.DivAssign:
f.RegisterRegister(asm.DIV, destination, source) f.RegisterRegister(asm.DIV, register, operand)
case token.Mod, token.ModAssign: case token.Mod, token.ModAssign:
f.RegisterRegister(asm.MODULO, destination, source) f.RegisterRegister(asm.MODULO, register, operand)
case token.And, token.AndAssign: case token.And, token.AndAssign:
f.RegisterRegister(asm.AND, destination, source) f.RegisterRegister(asm.AND, register, operand)
case token.Or, token.OrAssign: case token.Or, token.OrAssign:
f.RegisterRegister(asm.OR, destination, source) f.RegisterRegister(asm.OR, register, operand)
case token.Xor, token.XorAssign: case token.Xor, token.XorAssign:
f.RegisterRegister(asm.XOR, destination, source) f.RegisterRegister(asm.XOR, register, operand)
case token.Equal, token.NotEqual, token.Less, token.LessEqual, token.Greater, token.GreaterEqual: case token.Equal, token.NotEqual, token.Less, token.LessEqual, token.Greater, token.GreaterEqual:
f.RegisterRegister(asm.COMPARE, destination, source) f.RegisterRegister(asm.COMPARE, register, operand)
case token.Assign: case token.Assign:
f.RegisterRegister(asm.MOVE, destination, source) f.RegisterRegister(asm.MOVE, register, operand)
default: default:
return errors.New(&errors.InvalidOperator{Operator: operation.Text(f.File.Bytes)}, f.File, operation.Position) return errors.New(&errors.InvalidOperator{Operator: operation.Text(f.File.Bytes)}, f.File, operation.Position)

View File

@ -1,8 +1,6 @@
package core package core
import ( import (
"fmt"
"git.akyoto.dev/cli/q/src/build/asm" "git.akyoto.dev/cli/q/src/build/asm"
"git.akyoto.dev/cli/q/src/build/cpu" "git.akyoto.dev/cli/q/src/build/cpu"
"git.akyoto.dev/cli/q/src/build/errors" "git.akyoto.dev/cli/q/src/build/errors"
@ -36,10 +34,8 @@ func (f *Function) TokenToRegister(t token.Token, register cpu.Register) error {
return nil return nil
case token.String: case token.String:
f.count.data++ data := t.Bytes(f.File.Bytes)[1 : t.Length-1]
label := fmt.Sprintf("%s_data_%d", f.Name, f.count.data) label := f.AddBytes(data)
value := t.Bytes(f.File.Bytes)[1 : t.Length-1]
f.Assembler.SetData(label, value)
f.RegisterLabel(asm.MOVE, register, label) f.RegisterLabel(asm.MOVE, register, label)
return nil return nil